Modern integrated circuits have become very complex, frequently comprising literally millions of transistors. Microprocessors are a good example of integration of a complicated digital system, including memory, on a single chip. Moreover, the use of standard "cores"--optimized and well-defined circuit building blocks--together with application-specific logic, interface and other elements, supports rapid design of entire proprietary systems on a single ASIC (application specific integrated circuit), with marked advantages in reduced pin count, system size, power consumption, cost, etc. in various computer, communications and consumer applications.
Design and Simulation
The design of a digital IC involves many steps, some of them iterative. Generally, a designer begins defining a logic circuit at a behavioral level, for example using logical and mathematical structures like "a&lt;b*c"--similar to statements in many programming languages. A behavioral definition can include loops, e.g.:
while a&lt;c do PA1 begin PA1 d&lt;log(sig1) PA1 result&lt;=d 2 PA1 end PA1 for i=1 to max-count do PA1 begin . . . PA1 One signal can only change state at one fixed time offset to the clock signal for one test block; PA1 One signal can not change state more than twice in one clock cycle (e.g. 0-1-0 or 1-0-1); PA1 One pin cannot be driven and it's output compared at the same time (bidirect conflict error); PA1 There are only a limited number of timing generators available on the tester (One timing generator is occupied by a signal or a group of signals with a certain start time and waveform.); and PA1 The first pattern has to be X (unknown) for all inputs and Z (high impedance) for any bidirectional terminals (bidirects). PA1 Test vector size is limited PA1 Number of test vectors is limited PA1 Maximum clock speed for testing is limited PA1 Not all testers accept scan vectors
and so forth, where "sig1" may be a signal defined in the model. This behavioral level design is independent of any particular integrated circuit process or technology, and indeed is independent of logic gates or other real-world devices. The behavioral design is captured and described in a software model or file using a predetermined, standard format or "language". One example of a behavioral model is an RTL--register transfer level--description. In this description, we will refer to the behavioral level model as an RTL model although various other coding styles are known. Next, the RTL model is input to an RTL Simulator to simulate its operation and thereby confirm that it behaves functionally as intended. Examples of commercially available RTL simulators are those licensed by Cadence, Synopsis and Mentor Graphics.
The simulation is carried out using a "test bench". This is not a physical "bench" at all; rather, it is a software environment that includes the RTL or other behavioral level description of the circuit; a set of inputs or stimulae created by the designer for exercising the circuit; and a corresponding set of expected outputs or results. The test bench is written by the designer and is usually in the ascii format. Usually it contains only the logic levels (conditions) of the inputs. The designer will check the waveform to make sure the circuit behaves as expected. In cases where the designer knows the expected outputs, he/she can list the expected outputs in a separate file and the test bench can call for that file to conduct a simulation comparison and report the mismatches.
After simulation and test program/test pattern generation, the original test bench then becomes the test pattern containing vectors (still in ascii format) in the required format for the target tester. Only after the pattern is compiled on the tester, it is converted to to binary format. The test bench interfaces with and executes the simulator. The RTL simulator executes the circuit model in software, and in doing so outputs (1) a log file; (2) warnings; and (3) results of the simulation as compared to expected outputs. Another form of output from a simulator is data which can be viewed by a waveform viewer. The log file is a complete record of every change in every node value. It is sometimes called a vcd file--value change dump. The designer examines the simulation output, and makes adjustments to the design as required. The behavioral model is updated accordingly, and the simulation is repeated as required until the design at least meets the functional requirements. The test bench may also require modification. Once the simulation operates as expected, the functional design is approved, the system is ready for logic synthesis.
Logic Synthesis
Synthesis software receives the behavioral model, e.g. RTL code and converts it into a "gate-level" circuit design or "netlist", based on libraries of circuit descriptions in a given technology or process. Easier said than done, this step requires sophisticated software running on powerful workstations and is generally time consuming. The synthesis work is supported by software "libraries" defining individual gates, and higher level circuits or "cells". The libraries contain logical "behavioral" as well as detailed electrical specifications, sometimes called "models".
After completion of synthesis, the netlist is checked for design rule and timing compliance. The gate libraries may include timing specifications as well, or separate timing modeling software can be used for timing analysis. Next, gate level simulation is conducted, using essentially the same test bench as was written previously for testing the RTL level design.
Each semiconductor manufacturer has additional software, generally proprietary, for taking the completed netlist and generating the further detailed specifications, mask, etc. for actually fabricating the parts on silicon. Fabrication of the parts of course takes a great deal of time and specialized equipment. Any changes in the design at this late stage are very expensive and time consuming to implement. Every effort must be made to ensure working silicon the first time. In any event, after first silicon devices are made, they must be tested.
Device Testing
Testing, specifically digital integrated circuit testing, is carried out using special hardware "testers". Commercially available hardware testers include those made or licensed by Credence (e.g. "Logic 100", "STS"and "SC212"), Schlumberger and Teradyne to name a few. These logic testers are programmable and operate under control of specific test programs developed for testing the specific device at hand. Automatic test program generators are known for generating such test programs for a given target tester based on the netlist and the test bench provided as inputs. More specifically, output from the simulation (containing test bench information) is included among inputs to the test program generator.
Since the designer already created a test bench--a definition of inputs and outputs for verifying the behavioral design, the corresponding simulation can be ported to the hardware tester to test the silicon device. Thus, the test bench and the netlist are input to the automatic test program generator. However, each hardware tester imposes certain limitations and requirements on the test program. Therefore, as a practical matter, only a subset of all possible ways to stimulate a device can be ported to a tester. Those constraints include, but are not limited to the following:
If the simulation violates any of these criteria, the automated test generation will fail, or if a test program is generated, it will fail to work on the logic tester. At this late date in the design cycle, the designer is forced to go backward and revise the test bench so that a hardward test program can be generated. Changes this late in the design process are costly. Problems in testing may not be discovered until expert test engineers analyse failed test results. What is needed is to anticipate and accommodate testing limitations earlier in the design cycle.